Superconductor electronics is often considered to be a potential alternative to CMOS in the field of high-performance computing (HPC). The primary reasons for this are:
a) desire to lower the electric power footprint in HPC from ~100 MW per Exaflop/s (extrapolation of the current CMOS trends) to at least 10 times lower with superconductivity (including cryocooling overhead);
b) desire to improve single-thread performance of CMOS microprocessors from 1-2 Gcycles/s (yielding 2-4 GHz clock frequency with typical 2-thread operation) to over 10 Gcycles/s with superconductivity.

These high expectations for superconducting logic arise from its well-known ability to operate with record low energy dissipation (e.g., below 100 kT per logic operation in phase-mode logic known as AQFP) as well as with record high clock frequency (100+ GHz) demonstrated with pulse-mode logic such as RSFQ. While energy dissipation of the pulse-based logic is generally higher (about 5,000 kT per logic operation, regardless of the operation speed), it is still highly competitive with CMOS logic, where in most cases it exceeds 1,000,000 kT per logic operation, the bulk of which comes from long wiring interconnects between the gates. In contrast to CMOS, pulse-based logic can operate with nearly zero-power long interconnects using superconducting passive transmission lines (PTLs), where picosecond pulses can propagate ballistically.

 

In the talk, I will discuss major design challenges facing practical implementation of VLSI superconducting digital circuits that are visible to me due to my significant experience with both CMOS and superconducting circuit design, but are not commonly discussed in  superconducting community. They include:
a) the issues of design scalability towards finer technology nodes, e.g., avoidance of non-scalable circuit elements like transformers in digital designs;
b) practical design density, measured in Josephson junctions (JJs) per gate unit area vs FETs per gate unit area in the same technology node;
c) gate complexity (in JJs vs FETs per typical logic gate);
d) practical issues of bias current delivery to RSFQ chips;
e) and last, but not the least, poor compatibility of the existing superconducting logic families with standard VLSI CMOS digital design flow.

 

I will explain that the latter problem calls for development of a new clock-free pulse-based logic (DSFQ) that I originally presented at the ASC 2018 and will cover it in more detail at the end of my talk. 

 

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